
`timescale 1 ns / 1 ps

module fusion_S00_AXI #(
    parameter integer  FRAME_BUFFER_BASE    = 'h30000000,
    parameter integer  FRAME_BUFFER_SIZE    = 'h00200000,
    parameter integer  C_S_AXI_DATA_WIDTH   = 32,
    parameter integer  C_S_AXI_ADDR_WIDTH   = 16
) (
    input  wire                                 REGS_AXI_ACLK,
    input  wire                                 REGS_AXI_ARESETN,
    input  wire [C_S_AXI_ADDR_WIDTH-1 : 0     ] REGS_AXI_AWADDR,
    input  wire [2 : 0                        ] REGS_AXI_AWPROT,
    input  wire                                 REGS_AXI_AWVALID,
    output wire                                 REGS_AXI_AWREADY,
    input  wire [C_S_AXI_DATA_WIDTH-1 : 0     ] REGS_AXI_WDATA,
    input  wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0 ] REGS_AXI_WSTRB,
    input  wire                                 REGS_AXI_WVALID,
    output wire                                 REGS_AXI_WREADY,
    output wire [1 : 0                        ] REGS_AXI_BRESP,
    output wire                                 REGS_AXI_BVALID,
    input  wire                                 REGS_AXI_BREADY,
    //-------------------------------------------------------- 
    input  wire [C_S_AXI_ADDR_WIDTH-1 : 0     ] REGS_AXI_ARADDR,
    input  wire [2 : 0                        ] REGS_AXI_ARPROT,
    input  wire                                 REGS_AXI_ARVALID,
    output wire                                 REGS_AXI_ARREADY,
    output wire [C_S_AXI_DATA_WIDTH-1 : 0     ] REGS_AXI_RDATA,
    output wire [1 : 0                        ] REGS_AXI_RRESP,
    output wire                                 REGS_AXI_RVALID,
    input  wire                                 REGS_AXI_RREADY,
    //--------------------------------------------------------
    output reg  [31:0                         ] pix_cnt, 
    output reg  [7:0                          ] menu_alpha,
    output reg  [7:0                          ] disp_graym,
    
    output reg                                  mm_disp_en,
    output reg                                  mm_menu_en,
    output reg                                  mm_bar_hide,
    //--------------------------------------------------------
    input  wire [31:0]                          fusion_push_state,
    input  wire [31:0]                          fusion_proc_state,
    output reg  [31:0]                          fusion_base_x,
    output reg  [7:0]                           fusion_pix_black, 
    output reg  [31:0]                          fusion_push_ctrl,
    output reg  [7:0]                           fusion_face_sens,
    output reg  [7:0]                           fusion_edge_sens,
    output reg  [11:0]                          fusion_fast_l_x,
    output reg  [11:0]                          fusion_slow_l_x,
    output reg  [11:0]                          fusion_fast_r_x,
    output reg  [11:0]                          fusion_slow_r_x,
    output reg  [31:0]                          fusion_force_cfg,
    output reg  [31:0]                          fusion_time_cfg,

    input  wire [15:0]                          pix0_rang1_face_angle,
    input  wire [15:0]                          pix0_rang2_face_angle,
    input  wire [31:0]                          pix0_rang0_edge_accum,
    input  wire [31:0]                          pix0_rang1_edge_accum,
    input  wire [31:0]                          pix0_rang2_edge_accum,
    input  wire [31:0]                          pix0_rang3_edge_accum,
    input  wire [31:0]                          pix0_rang1_bold_accum,
    input  wire [31:0]                          pix0_rang2_bold_accum,
    input  wire [31:0]                          pix0_rang1_core_accum,
    input  wire [31:0]                          pix0_rang2_core_accum,

    input  wire [15:0]                          pix1_rang1_face_angle,
    input  wire [15:0]                          pix1_rang2_face_angle,
    input  wire [31:0]                          pix1_rang0_edge_accum,
    input  wire [31:0]                          pix1_rang1_edge_accum,
    input  wire [31:0]                          pix1_rang2_edge_accum,
    input  wire [31:0]                          pix1_rang3_edge_accum,
    input  wire [31:0]                          pix1_rang1_bold_accum,
    input  wire [31:0]                          pix1_rang2_bold_accum,
    input  wire [31:0]                          pix1_rang1_core_accum,
    input  wire [31:0]                          pix1_rang2_core_accum,

    input  wire [31:0]                          fiber_push_status,
    output reg  [31:0]                          fiber_aux_ctrl,
    //--------------------------------------------------------
    output reg                                  SDIO_0_wp,
    output reg                                  force_pwr_off,
    output reg                                  vga_pwr_off,
    
    output reg                                  xadc_init,
    input  wire [15:0]                          temp_value,   
    input  wire [15:0]                          vpin_value,  
    input  wire [15:0]                          vtmp_value,
    input  wire [15:0]                          vint_value,   
    input  wire [15:0]                          vaux_value,   

    input  wire                                 soft_pwr_off,
    input  wire [7:0 ]                          touch_status,
    output reg                                  video0_only,   
    output reg                                  video1_only,   
    output wire [31:0                         ] video0_base_addr,
    output wire [31:0                         ] video1_base_addr,
    output reg  [31:0                         ] menu_base_addr,
    //--------------------------------------------------------
    output reg                                  camera0_video_en,
    output reg  [23:0                         ] camera0_dsp_ctrl,
    output reg  [31:0                         ] camera0_pwr_ctrl,
    output reg  [31:0                         ] camera0_ctrl,
    input  wire [15:0                         ] camera0_data_read,
    input  wire                                 camera0_trans_over,
    input  wire [31:0                         ] camera0_param, 
    input  wire [31:0                         ] camera0_error,    
    input  wire                                 camera0_base_update, //sync with IDLE stat
    output wire [31:0                         ] camera0_base_addr,
    output reg  [15:0                         ] camera0_x_org_cnt,
    output reg  [15:0                         ] camera0_y_org_cnt,
    output reg  [15:0                         ] camera0_x_scaler ,
    output reg  [15:0                         ] camera0_y_scaler ,  
    input  wire [15:0                         ] camera0_cfg_state ,  
    //--------------------------------------------------------
    output reg                                  camera1_video_en,
    output reg  [23:0                         ] camera1_dsp_ctrl,      
    output reg  [31:0                         ] camera1_pwr_ctrl    ,
    output reg  [31:0                         ] camera1_ctrl,
    input  wire [15:0                         ] camera1_data_read,
    input  wire                                 camera1_trans_over,
    input  wire [31:0                         ] camera1_param,
    input  wire [31:0                         ] camera1_error,     
    input  wire                                 camera1_base_update, //sync with IDLE stat
    output wire [31:0                         ] camera1_base_addr,
    output reg  [15:0                         ] camera1_x_org_cnt,
    output reg  [15:0                         ] camera1_y_org_cnt,
    output reg  [15:0                         ] camera1_x_scaler ,
    output reg  [15:0                         ] camera1_y_scaler ,  
    input  wire [15:0                         ] camera1_cfg_state ,  
    //--------------------------------------------------------
    output reg  [31:0                         ] motor_speed,
    output reg  [31:0                         ] motor_ctrl_l,
    output reg  [31:0                         ] motor_ctrl_r,
    output reg  [31:0                         ] motor_ctrl_x,
    output reg  [31:0                         ] motor_ctrl_y,
 
    output reg  [31:0                         ] gaoya_time, 
    output reg  [7:0                          ] gaoya_force, 
    output reg                                  heat_mode, 
    output reg                                  heat_test,
    input  wire                                 heat_status,
    output reg  [7:0                          ] heat_speed, 
    output reg  [15:0                         ] heat_time, 
    output reg  [31:0                         ] beep_cntr, 
    output reg  [31:0                         ] tone_divider, 
    output reg  [31:0                         ] rtc_ctrl, 
    input  wire [15:0                         ] rtc_data_read, 
    input  wire                                 rtc_trans_over, 
    output reg                                  load_time, 

    output reg  [31:0                         ] pcf8563_date      , 
    output reg  [31:0                         ] pcf8563_time      , 
    input  wire [31:0                         ] local_date        , 
    input  wire [31:0                         ] local_time        , 
    output reg  [31:0                         ] eeprom_ctrl       , 
    input  wire [15:0                         ] eeprom_data_read  , 
    input  wire                                 eeprom_trans_over , 

    output reg  [7:0                          ] backlight_pwm_ctnr,
    input  wire [31:0]                          hardware_version,
    input  wire [31:0                         ] data_flow_err,   
    input  wire                                 pwr_touch,    
    input  wire [10:0                         ] plh_keys,
    output reg  [10:0]                          func_keys,
    input  wire [31:0]                          calibera_edge_x ,
    input  wire [31:0]                          calibera_edge_y ,
    input  wire [31:0]                          engineer_edge_x ,
    input  wire [31:0]                          engineer_edge_y ,
    input  wire [31:0]                          engineer_bright ,
    output reg  [11:0]                          cpu_mem_addrb,
    input  wire [31:0]                          cpu_mem_doutb,
    input  wire                                 cpu_mem_ready0,
    input  wire                                 cpu_mem_ready1
);
 
//--------------------------------------------------------
localparam ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam OPT_MEM_ADDR_BITS = 13;
`ifdef SIMULATION
    localparam PIX_SIZE = 64*48;
    localparam PIX_XCNT = 64;
    localparam PIX_YCNT = 48;
`else
    localparam PIX_SIZE = 640*480;
    localparam PIX_XCNT = 640;
    localparam PIX_YCNT = 480;
`endif

//wire[31:0] hardware_version = {HSEG3[7:0],HSEG2[7:0],HSEG1[7:0],HSEG0[7:0]};
//--------------------------------------------------------
reg [C_S_AXI_ADDR_WIDTH-1 : 0 ] axi_awaddr;
reg                             axi_awready;
reg                             axi_wready;
reg [1 : 0                    ] axi_bresp;
reg                             axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0 ] axi_araddr;
reg                             axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0 ] axi_rdata;
reg [1 : 0                    ] axi_rresp;
reg                             axi_rvalid;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg20;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0]    slv_reg22;
wire                            camera0_resetn;
wire                            camera0_pwrdown;
wire                            camera1_resetn;
wire                            camera1_pwrdown;
reg [C_S_AXI_DATA_WIDTH-1:0]    reg_data_out;
wire                            slv_reg_rden;
wire                            slv_reg_wren;
integer                         byte_index;
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 )  begin
        axi_awready <= 1'b0;
    end 
    else begin    
        if (~axi_awready && REGS_AXI_AWVALID && REGS_AXI_WVALID) begin
            axi_awready <= 1'b1;
        end
        else begin
            axi_awready <= 1'b0;
        end
    end 
end       
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK )begin
    if ( REGS_AXI_ARESETN == 1'b0 )begin
        axi_awaddr <= 0;
    end 
    else if (~axi_awready && REGS_AXI_AWVALID && REGS_AXI_WVALID) begin
        axi_awaddr <= REGS_AXI_AWADDR;
    end 
end       
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin 
    if ( REGS_AXI_ARESETN == 1'b0 ) begin 
        axi_wready <= 1'b0;
    end
    else begin 
        if (~axi_wready && REGS_AXI_WVALID && REGS_AXI_AWVALID) begin 
            axi_wready <= 1'b1;
        end
        else begin 
            axi_wready <= 1'b0;
        end
    end 
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        axi_bvalid <= 0;
        axi_bresp <= 2'b0;
    end
    else begin
        if (axi_awready && REGS_AXI_AWVALID && ~axi_bvalid && axi_wready && REGS_AXI_WVALID) begin
            axi_bvalid <= 1'b1;
            axi_bresp <= 2'b0; // 'OKAY' response
        end // work error responses in future
        else begin
            if (REGS_AXI_BREADY && axi_bvalid) begin
                axi_bvalid <= 1'b0;
            end
        end
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        axi_arready    <= 1'b0;
        axi_araddr     <= 32'b0;
        cpu_mem_addrb  <= 12'b0;
    end
    else begin
        if (~axi_arready && REGS_AXI_ARVALID) begin
            axi_arready    <= 1'b1;
            axi_araddr     <= REGS_AXI_ARADDR[15:0];
            cpu_mem_addrb  <= REGS_AXI_ARADDR[13:2];
        end
        else begin
            axi_arready <= 1'b0;
        end
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        axi_rvalid <= 0;
        axi_rresp <= 0;
    end
    else if (axi_arready && REGS_AXI_ARVALID && ~axi_rvalid) begin
        axi_rvalid <= 1'b1;
        axi_rresp  <= 2'b0; // 'OKAY' response
    end
    else begin
        axi_rvalid <= 1'b0;
    end
end
//--------------------------------------------------------
reg axi_rvalid_ff1;
reg axi_rvalid_ff2;
reg axi_rvalid_ff3;
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) axi_rvalid_ff1 <= axi_rvalid;
always @( posedge REGS_AXI_ACLK ) axi_rvalid_ff2 <= axi_rvalid_ff1;
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        axi_rvalid_ff3 <= 1'b0;
    end
    else if(axi_rvalid_ff2)begin
        axi_rvalid_ff3 <= 1'b1;
    end    
    else if(REGS_AXI_RREADY)begin
        axi_rvalid_ff3 <= 1'b0;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        axi_rdata <= 0;
    end
    else begin
        if (slv_reg_rden) begin
            axi_rdata <= reg_data_out; // register read data
        end
    end
end
//--------------------------------------------------------
assign slv_reg_rden = axi_rvalid_ff2;
assign slv_reg_wren = axi_wready && REGS_AXI_WVALID && axi_awready && REGS_AXI_AWVALID;
//--------------------------------------------------------
//------
//------   register assignment
//------
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera0_ctrl <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd0)) begin
        camera0_ctrl <= REGS_AXI_WDATA;
    end
    else if(camera0_ctrl[31]&&camera0_trans_over) begin 
        camera0_ctrl[31] <= 1'b0;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera0_video_en  <= 0;
        camera0_dsp_ctrl  <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd2)) begin
        camera0_video_en  <= REGS_AXI_WDATA[31];
        camera0_dsp_ctrl  <= REGS_AXI_WDATA[23:0];              
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg3   <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd3)) begin
        slv_reg3   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg4   <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*1;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd4)) begin
        slv_reg4   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg5   <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*2;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd5)) begin
        slv_reg5   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera0_x_org_cnt <= PIX_XCNT;
        camera0_y_org_cnt <= PIX_YCNT;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd6)) begin
        camera0_x_org_cnt <= REGS_AXI_WDATA[15:0];
        camera0_y_org_cnt <= REGS_AXI_WDATA[31:16];     
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera0_x_scaler <= 16'h1;
        camera0_y_scaler <= 16'h2;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd7)) begin
        camera0_x_scaler <= REGS_AXI_WDATA[15:0];
        camera0_y_scaler <= REGS_AXI_WDATA[31:16];
    end
end

//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera0_pwr_ctrl <= 32'b1;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd9)) begin
        camera0_pwr_ctrl  <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera1_ctrl <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd10)) begin
        camera1_ctrl <= REGS_AXI_WDATA;
    end
    else if(camera1_ctrl[31]&&camera1_trans_over) begin 
        camera1_ctrl[31] <= 1'b0;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera1_video_en  <= 0;
        camera1_dsp_ctrl  <= 0;       
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd12)) begin
        camera1_video_en  <= REGS_AXI_WDATA[31];
        camera1_dsp_ctrl  <= REGS_AXI_WDATA[23:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg13   <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*3;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd13)) begin
        slv_reg13   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg14   <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*4;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd14)) begin
        slv_reg14   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg15   <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*5;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd15)) begin
        slv_reg15   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera1_x_org_cnt <= PIX_XCNT;
        camera1_y_org_cnt <= PIX_YCNT;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd16)) begin
        camera1_x_org_cnt <= REGS_AXI_WDATA[15:0];
        camera1_y_org_cnt <= REGS_AXI_WDATA[31:16];     
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera1_x_scaler <= 16'h1;
        camera1_y_scaler <= 16'h2;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd17)) begin
        camera1_x_scaler <= REGS_AXI_WDATA[15:0];
        camera1_y_scaler <= REGS_AXI_WDATA[31:16];
    end
end

//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        camera1_pwr_ctrl  <= 32'b0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd19)) begin
        camera1_pwr_ctrl <= REGS_AXI_WDATA;
    end
end

//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg20   <= 32'h20000000;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd20)) begin
        slv_reg20   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg21   <= 32'h20200000;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd21)) begin
        slv_reg21   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        slv_reg22   <= 32'h20400000;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd22)) begin
        slv_reg22   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
reg[1:0] mm_menu_sel ;
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        mm_menu_sel  <= 2'b0;
        mm_bar_hide  <= 1'b0;
        mm_menu_en   <= 1'b1;
        mm_disp_en   <= 1'b1;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd23)) begin
        mm_menu_sel  <= REGS_AXI_WDATA[9:8];
        mm_bar_hide  <= REGS_AXI_WDATA[2];
        mm_menu_en   <= REGS_AXI_WDATA[1];
        mm_disp_en   <= REGS_AXI_WDATA[0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        pix_cnt   <= PIX_SIZE;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd24)) begin
        pix_cnt   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        menu_alpha   <= 8'hff;
        disp_graym   <= 8'hff;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd25)) begin
        menu_alpha   <= REGS_AXI_WDATA[7:0];
        //disp_graym   <= {1'b1,REGS_AXI_WDATA[22:16]};
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        backlight_pwm_ctnr  <= 8'hff;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd26)) begin
        backlight_pwm_ctnr  <= REGS_AXI_WDATA[7:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        motor_speed   <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd30)) begin
        motor_speed   <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        motor_ctrl_l  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd31)) begin
        motor_ctrl_l  <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        motor_ctrl_r  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd32)) begin
        motor_ctrl_r  <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        motor_ctrl_x  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd33)) begin
        motor_ctrl_x  <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        motor_ctrl_y  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd34)) begin
        motor_ctrl_y  <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        gaoya_time   <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd40)) begin
        gaoya_time   <= REGS_AXI_WDATA;
    end
    else if(gaoya_time > 0) begin
        gaoya_time   <= gaoya_time - 1;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        gaoya_force   <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd41)) begin
        gaoya_force   <= REGS_AXI_WDATA[7:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        heat_test   <= 1'b0;
        heat_mode   <= 1'b0;
        heat_speed  <= 8'h2;
        heat_time   <= 30000;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd42)) begin
        heat_test   <= REGS_AXI_WDATA[25];
        heat_mode   <= REGS_AXI_WDATA[24];
        heat_speed  <= REGS_AXI_WDATA[23:16];
        heat_time   <= REGS_AXI_WDATA[15:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        beep_cntr  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd43)) begin
        beep_cntr  <= REGS_AXI_WDATA[31:0];
    end
    else if(beep_cntr > 0) begin
        beep_cntr  <= beep_cntr - 1;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        tone_divider  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd44)) begin
        tone_divider  <= REGS_AXI_WDATA[31:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        rtc_ctrl <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd45)) begin
        rtc_ctrl <= REGS_AXI_WDATA;
    end
    else if(rtc_ctrl[31]&&rtc_trans_over) begin 
        rtc_ctrl[31] <= 1'b0;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        load_time <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd47)) begin
        load_time <= REGS_AXI_WDATA;
    end
    else if(load_time == 1'b1)begin
        load_time <= 1'b0;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        pcf8563_date  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd48)) begin
        pcf8563_date  <= REGS_AXI_WDATA[31:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        pcf8563_time  <= 'h0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd49)) begin
        pcf8563_time  <= REGS_AXI_WDATA[31:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        eeprom_ctrl <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd52)) begin
        eeprom_ctrl <= REGS_AXI_WDATA;
    end
    else if(eeprom_ctrl[31]&&eeprom_trans_over) begin 
        eeprom_ctrl[31] <= 1'b0;
    end
end 

//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        video0_only <= 'b0;
        video1_only <= 'b0; 
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd55)) begin
        video0_only <= REGS_AXI_WDATA[0];    
        video1_only <= REGS_AXI_WDATA[1];    
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        func_keys <= 'h7ff;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd60)) begin
        func_keys <= REGS_AXI_WDATA[10:0];     
    end
    // FUSION_V1
    //else begin
    //    func_keys <= {pwr_touch,plh_keys[10:0]};
    //end
end
//--------------------------------------------------------
reg[11:0] fusion_key_touch;
always @( posedge REGS_AXI_ACLK )  fusion_key_touch <= {pwr_touch,plh_keys[10:0]};
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_force_cfg <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd62)) begin
        fusion_force_cfg <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_time_cfg <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd63)) begin
        fusion_time_cfg <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_push_ctrl <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd70)) begin
        fusion_push_ctrl <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_base_x <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd71)) begin
        fusion_base_x <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_face_sens <= 0;
        fusion_edge_sens <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd73)) begin
        fusion_face_sens <= REGS_AXI_WDATA[7:0];
        fusion_edge_sens <= REGS_AXI_WDATA[15:8];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_pix_black <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd74)) begin
        fusion_pix_black <= REGS_AXI_WDATA[7:0];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fiber_aux_ctrl <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd75)) begin
        fiber_aux_ctrl <= REGS_AXI_WDATA;
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_fast_l_x <= 0;
        fusion_slow_l_x <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd77)) begin
        fusion_fast_l_x <= REGS_AXI_WDATA[11:0];
        fusion_slow_l_x <= REGS_AXI_WDATA[27:16];
    end
end
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_fast_r_x <= 0;
        fusion_slow_r_x <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd78)) begin
        fusion_fast_r_x <= REGS_AXI_WDATA[11:0];
        fusion_slow_r_x <= REGS_AXI_WDATA[27:16];
    end
end 
//-------------------------------------------------------- 
reg disp_pwr_off;
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        SDIO_0_wp     <= 0;
        force_pwr_off <= 0;
        disp_pwr_off  <= 0; 
        xadc_init     <= 0;     
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd110))begin
        SDIO_0_wp     <= REGS_AXI_WDATA[0];
        force_pwr_off <= REGS_AXI_WDATA[1];
        disp_pwr_off  <= REGS_AXI_WDATA[2]; 
        xadc_init     <= REGS_AXI_WDATA[3];         
    end
end  
//--------------------------------------------------------   
reg[31:0] fusion_unid0;
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_unid0 <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd180))begin
        fusion_unid0 <= REGS_AXI_WDATA;    
    end
end  
//--------------------------------------------------------
reg[31:0] fusion_unid1;
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) begin
    if ( REGS_AXI_ARESETN == 1'b0 ) begin
        fusion_unid1 <= 0;
    end
    else if (slv_reg_wren &&( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 16'd181))begin
        fusion_unid1 <= REGS_AXI_WDATA;    
    end
end  
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) vga_pwr_off <= ~disp_pwr_off;
//--------------------------------------------------------
//----
//----  Local logic
//----
//--------------------------------------------------------
reg[31:0] flow_err;
always @( posedge REGS_AXI_ACLK ) flow_err    <= data_flow_err;
//--------------------------------------------------------
wire[C_S_AXI_DATA_WIDTH*3 -1 : 0] menu_reg_group = {slv_reg22,slv_reg21,slv_reg20};
//--------------------------------------------------------
always @( posedge REGS_AXI_ACLK ) menu_base_addr <= menu_reg_group[(C_S_AXI_DATA_WIDTH*mm_menu_sel ) +: C_S_AXI_DATA_WIDTH];    
//--------------------------------------------------------
reg[1:0] video0_wr_ptr;
reg[1:0] video0_rd_ptr;
//--------------------------------------------------------
always @(posedge REGS_AXI_ACLK) begin
    if(~REGS_AXI_ARESETN)begin 
        video0_wr_ptr <= 2'h0; 
        video0_rd_ptr <= 2'h2; // protection gap == 1
    end 
    else if(camera0_base_update) begin
        video0_wr_ptr <= (video0_wr_ptr < 2)?(video0_wr_ptr + 1):2'h0;
        video0_rd_ptr <= (video0_rd_ptr < 2)?(video0_rd_ptr + 1):2'h0;
    end 
end 
//--------------------------------------------------------
wire[C_S_AXI_DATA_WIDTH*3 -1 : 0] slv_reg_group0 = {slv_reg5,slv_reg4,slv_reg3};
reg[C_S_AXI_DATA_WIDTH -1 : 0]    video0_write_base_addr;
reg[C_S_AXI_DATA_WIDTH -1 : 0]    video0_read_base_addr ;
//--------------------------------------------------------
always @(posedge REGS_AXI_ACLK) begin
    if(~REGS_AXI_ARESETN)begin 
        video0_write_base_addr <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*2;
        video0_read_base_addr  <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*0;
    end 
    else if(camera0_base_update) begin 
        video0_write_base_addr <= slv_reg_group0[(C_S_AXI_DATA_WIDTH * video0_wr_ptr) +: C_S_AXI_DATA_WIDTH];
        video0_read_base_addr  <= slv_reg_group0[(C_S_AXI_DATA_WIDTH * video0_rd_ptr) +: C_S_AXI_DATA_WIDTH];
    end 
end 
//--------------------------------------------------------
assign  camera0_base_addr = video0_write_base_addr;
assign  video0_base_addr  = video0_read_base_addr;
//--------------------------------------------------------
reg[1:0] video1_wr_ptr;
reg[1:0] video1_rd_ptr;
//--------------------------------------------------------
always @(posedge REGS_AXI_ACLK) begin
    if(~REGS_AXI_ARESETN)begin 
        video1_wr_ptr <= 2'h0; 
        video1_rd_ptr <= 2'h2; // protection gap == 1
    end 
    else if(camera1_base_update) begin
        video1_wr_ptr <= (video1_wr_ptr < 2)?(video1_wr_ptr + 1):2'h0;
        video1_rd_ptr <= (video1_rd_ptr < 2)?(video1_rd_ptr + 1):2'h0;
    end 
end 
//--------------------------------------------------------
wire[C_S_AXI_DATA_WIDTH*3 -1 : 0] slv_reg_group1 = {slv_reg15,slv_reg14,slv_reg13};
reg[C_S_AXI_DATA_WIDTH -1 : 0]    video1_write_base_addr;
reg[C_S_AXI_DATA_WIDTH -1 : 0]    video1_read_base_addr ;
//--------------------------------------------------------
always @(posedge REGS_AXI_ACLK) begin
    if(~REGS_AXI_ARESETN)begin 
        video1_write_base_addr <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*5;
        video1_read_base_addr  <= FRAME_BUFFER_BASE + FRAME_BUFFER_SIZE*3;
    end 
    else if(camera1_base_update) begin 
        video1_write_base_addr <= slv_reg_group1[(C_S_AXI_DATA_WIDTH * video1_wr_ptr) +: C_S_AXI_DATA_WIDTH];
        video1_read_base_addr  <= slv_reg_group1[(C_S_AXI_DATA_WIDTH * video1_rd_ptr) +: C_S_AXI_DATA_WIDTH];
    end 
end 
//--------------------------------------------------------
assign  camera1_base_addr = video1_write_base_addr;
assign  video1_base_addr  = video1_read_base_addr;
//--------------------------------------------------------
//--  0~9   camera0 
//--  10~19 camera1 
//--  20~29 vga 
//--  30~39 motor
//--  40~59 accessory
//--  60~64 global
//--------------------------------------------------------
always @(*) begin
    case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
        16'd00: reg_data_out = camera0_ctrl;
        16'd01: reg_data_out = {16'd0,camera0_data_read[15:0]};
        16'd02: reg_data_out = {camera0_video_en,7'b0,camera0_dsp_ctrl};
        16'd03: reg_data_out = slv_reg3;
        16'd04: reg_data_out = slv_reg4;
        16'd05: reg_data_out = slv_reg5;
        16'd06: reg_data_out = camera0_param;
        16'd07: reg_data_out = {camera0_y_scaler,camera0_x_scaler};
        16'd08: reg_data_out = camera0_error;
        16'd09: reg_data_out = camera0_pwr_ctrl;

        16'd10: reg_data_out = camera1_ctrl;
        16'd11: reg_data_out = {16'd0,camera1_data_read[15:0]};
        16'd12: reg_data_out = {camera1_video_en,7'b0,camera1_dsp_ctrl};
        16'd13: reg_data_out = slv_reg13;
        16'd14: reg_data_out = slv_reg14;
        16'd15: reg_data_out = slv_reg15;
        16'd16: reg_data_out = camera1_param;
        16'd17: reg_data_out = {camera1_y_scaler,camera1_x_scaler};
        16'd18: reg_data_out = camera1_error;
        16'd19: reg_data_out = camera1_pwr_ctrl;
        
        16'd20: reg_data_out = slv_reg20;
        16'd21: reg_data_out = slv_reg21;
        16'd22: reg_data_out = slv_reg22;
        16'd23: reg_data_out = {22'b0,mm_menu_sel,5'h0,mm_bar_hide,mm_menu_en,mm_disp_en};
        16'd24: reg_data_out = pix_cnt;
        16'd25: reg_data_out = menu_alpha;
        16'd26: reg_data_out = backlight_pwm_ctnr;
        
        16'd30: reg_data_out = motor_speed ;
        16'd31: reg_data_out = motor_ctrl_l;
        16'd32: reg_data_out = motor_ctrl_r;
        16'd33: reg_data_out = motor_ctrl_x;
        16'd34: reg_data_out = motor_ctrl_y;

        16'd40: reg_data_out = gaoya_time;
        16'd41: reg_data_out = {24'b0,gaoya_force};
        16'd42: reg_data_out = {heat_status,6'b0,heat_mode,heat_speed,heat_time};
        16'd43: reg_data_out = beep_cntr;
        16'd44: reg_data_out = tone_divider;
        16'd45: reg_data_out = rtc_ctrl;
        16'd46: reg_data_out = {16'b0,rtc_data_read};
        16'd47: reg_data_out = {31'b0,load_time};
        16'd48: reg_data_out = pcf8563_date;
        16'd49: reg_data_out = pcf8563_time;
        16'd50: reg_data_out = local_date;
        16'd51: reg_data_out = local_time;
        16'd52: reg_data_out = eeprom_ctrl;
        16'd53: reg_data_out = {16'b0,eeprom_data_read};

        16'd55: reg_data_out = {30'b0,video1_only,video0_only};
        16'd60: reg_data_out = {20'h0,pwr_touch,func_keys[10:0]};
        16'd61: reg_data_out = {flow_err,19'b0,fusion_key_touch[11:0]};
        16'd62: reg_data_out = fusion_force_cfg; //{clean,pre,8'b0,splice}
        16'd63: reg_data_out = fusion_time_cfg;  //{clean,pre,splice[15:0]} *100000 (1/100 us)

        16'd70: reg_data_out = fusion_push_ctrl;
        16'd71: reg_data_out = fusion_base_x;
        16'd72: reg_data_out = {soft_pwr_off,23'b0,touch_status};
        16'd73: reg_data_out = {16'b0,fusion_edge_sens,fusion_face_sens};
        16'd74: reg_data_out = {24'b0,fusion_pix_black}; 
        16'd75: reg_data_out = fiber_aux_ctrl; 
        16'd77: reg_data_out = {4'b0,fusion_slow_l_x,4'b0,fusion_fast_l_x}; 
        16'd78: reg_data_out = {4'b0,fusion_slow_r_x,4'b0,fusion_fast_r_x}; 
                
        16'd80: reg_data_out = fusion_proc_state;
        16'd81: reg_data_out = fiber_push_status;
        16'd82: reg_data_out = fusion_push_state;
      	16'd83: reg_data_out = {camera1_cfg_state,camera0_cfg_state};

        16'd108:reg_data_out = {31'b0,cpu_mem_ready0};        
        16'd109:reg_data_out = {31'b0,cpu_mem_ready1};        
        16'd110:reg_data_out = {28'b0,xadc_init,disp_pwr_off,force_pwr_off,SDIO_0_wp};
        
        16'd111:reg_data_out = engineer_edge_x ;
        16'd112:reg_data_out = engineer_edge_y ;
        16'd113:reg_data_out = calibera_edge_x ;
        16'd114:reg_data_out = calibera_edge_y ;

        16'd118:reg_data_out = engineer_bright ;

        16'd160:reg_data_out = {16'b0,temp_value};
        16'd161:reg_data_out = {16'b0,vint_value};
        16'd162:reg_data_out = {16'b0,vaux_value};
        16'd163:reg_data_out = {16'b0,vpin_value};
        16'd164:reg_data_out = {16'b0,vtmp_value};
 
        16'd180:reg_data_out = {fusion_unid0};
        16'd181:reg_data_out = {fusion_unid1}; 
        
        16'd200:reg_data_out = hardware_version;


        default: 
            reg_data_out = cpu_mem_doutb; // mem read data
    endcase
end
//--------------------------------------------------------
assign {camera0_pwrdown,camera0_resetn} = camera0_pwr_ctrl[1:0];
assign {camera1_pwrdown,camera1_resetn} = camera1_pwr_ctrl[1:0];
//--------------------------------------------------------

assign REGS_AXI_AWREADY   = axi_awready;
assign REGS_AXI_WREADY    = axi_wready;
assign REGS_AXI_BRESP     = axi_bresp;
assign REGS_AXI_BVALID    = axi_bvalid;
assign REGS_AXI_ARREADY   = axi_arready;
assign REGS_AXI_RDATA     = axi_rdata;
assign REGS_AXI_RRESP     = axi_rresp;
assign REGS_AXI_RVALID    = axi_rvalid_ff3;
//--------------------------------------------------------

endmodule



